1. Technical Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a fabrication method thereof using a damascene gate process and a silicon epitaxial process to prevent a pad bridge due to a void of an inter-insulation layer, to reduce a contact resistance, and to ensure a sufficient overlay margin of a bit-line contact.
2. Description of the Related Art
Generally, as the size of semiconductor devices is reduced, the cell pitch is reduced as well. As the cell pitch is reduced, voids are generated due to gap-fill failures in inter-insulation layers, open-failures in cell contacts are generated, the contact resistance of individual cells are increased, and the overlay margin in a bit-line contact is reduced.
FIGS. 1A to 4A are cross-sectional views illustrating a fabrication process of a conventional semiconductor memory and FIGS. 1B, 2B, 3B, and 4B are plan views illustrating a fabrication process for the conventional semiconductor memory device, wherein FIGS. 1A, 2A, 3A, and 4A are cross-sectional views taken along a line IA-IA′ in FIG. 4B.
Referring to FIGS. 1A and 1B, a semiconductor substrate 100 is divided into a field region 101 and an active region 105. A conventional shallow trench isolation STI process is performed to form a field isolation region 110 in the field region 101 of the semiconductor substrate 100.
Referring to FIGS. 2A and 2B, a gate 120 crossing over the active region 105 is formed on the substrate 100. In other words, on the substrate 100, a gate insulation layer 121, a polysilicon layer 123, a tungsten (W) layer 125, and a cap nitride layer 127 are deposited sequentially and patterned using a gate mask (not shown) to form the gate 120. Spacers 130 composed of a nitride layer are formed on the sidewalls of the gate 120.
Referring to FIGS. 3A and 3B, a first inter-insulation layer 140 is deposited on the substrate 100 and a conventional self-aligned contact process is performed to form self-aligned contacts (SACs) 150. Sequentially, a conductive layer for a SAC contact pad, such as a polysilicon layer, is deposited and a chemical and mechanical polishing CMP process or an etch-back process is performed to form SAC contact pads 160.
Referring to FIG. 4A and FIG. 4B, a second inter-insulation layer 170 is deposited on the substrate 100 and patterned to form a bit-line contact 180. The bit-line contact exposes the corresponding contact pad of the SAC contact pads 160 which is to be connected with a bit-line in a subsequent process. In other conventional processes, such as processes for forming bit-lines, storage node contacts, capacitors, and metal interconnections, the steps are performed sequentially to fabricate the conventional dynamic random access memory DRAM device.
However, the conventional DRAM device fabrication method has the following problems due to the reduction of the cell pitch according to the size reduction of the DRAM device.
First, when gap-filling with the first inter-insulation layer occurs, a void due to a gap-fill failure may cause a bridge-failure between the pads. Secondly, the open area of the SAC contact 150 is reduced, generating an open-failure, and the cell contact resistance may increase due to the reduction in the contact area between the SAC contact pad 160 and the active region 105 caused by the surface treatment. Thirdly, the thickness of the gate spacer 130 is reduced, generating a leakage current between the gate 120 and the SAC contact pad 160. Finally, the overlay margin of the bit-line contact 180 is reduced.